A signal line is a conductor used to transmit electrical signals between the various devices in an electronic system. Output driver circuits contained on each device are used to buffer signals originating from the device so that they may be driven onto the signal line.
For example, FIG. 1 illustrates a prior art digital system 1 including a plurality of devices 2, a signal transmitting device 3 and a signal line 4. The transmitting device 3 contains an output driver circuit 5 that generates a single-ended signal for output onto the signal line 4. The devices 2 are connected to the signal line 4 at various points to receive the signal. The signal line 4 includes a conductor 12, a termination resistor R.sub.T and a termination voltage V.sub.Term. The termination resistor R.sub.T is connected to the end of the conductor 12 opposite the end connected to the output driver circuit 5. The termination resistor R.sub.T absorbs the incident signal, thereby preventing reflections of the signal from occurring at the end of the conductor 12. The termination resistor R.sub.T is also connected to the termination voltage V.sub.Term. The termination voltage V.sub.Term is used to raise the voltage of the conductor 12 to the high voltage level V.sub.oh.
An embodiment of the prior art digital system 1, a memory system 6, is shown in FIG. 2. Memory system 6 includes a plurality of dynamic random-access memories (DRAMs) 11, a clock chip 7, a clock line 8 and a memory controller 24. The clock chip 7 contains a clock driver circuit 9 that generates a single-ended clock signal for output onto the clock line 8. The clock line 8 includes a conductor 10 that passes through the memory controller 24 such that the conductor is divided into two portions: a CTM (clock to master) portion and a CFM (clock from master) portion. The CTM portion propagates the clock signal from the clock driver circuit 9 towards the memory controller 24 (the memory controller is the master device in the system). The CFM portion propagates the clock signal from the memory controller 24 towards the DRAMs 11. The DRAMs 11 are connected to both the CTM and CFM portions of the conductor 10. The conductor 10 is divided in this manner so that the clock signal can maintain a specific phase relationship with data signals (not shown) that are transmitted between the DRAMs 11 and the memory controller 24 as the signals propagate, regardless of whether the data signals are transmitted from the DRAMs to the memory controller or vice versa.
FIG. 3 shows a simplified electrical model of the clock driver circuit 9 and the clock line 8 in the memory system 6. In this model, the clock line 8 is represented by a transmission line of loaded impedance Z.sub.0. The loaded impedance Z.sub.0 includes the unloaded characteristic impedance Z.sub.0 ' of the conductor 10 as well as the impedance of the DRAMs 11 and any other devices connected to the conductor. In order to minimize clock signal reflections at the end of the conductor 10, the resistance of the termination resistor R.sub.T is typically set to equal the loaded impedance Z.sub.0 of the conductor.
FIG. 4 is a waveform diagram illustrating the clock signal produced by the clock driver circuit 9 as a function of time. The clock signal has a high voltage level V.sub.oh and a low voltage level V.sub.ol, where V.sub.oh =V.sub.Term. V.sub.ol =V.sub.Term -2*(V.sub.Term -V.sub.Ref), and V.sub.Ref is a reference voltage. As a result, the clock signal has a voltage swing V.sub.sw of V.sub.sw =2*(V.sub.Term -V.sub.Ref). The clock driver circuit 9 generates this waveform by operating as a switching current source, alternately turning on and off, sinking current every other half-cycle of the clock period. The clock signal is converted into an internal clock signal for use within the DRAMs 11 by circuitry (not shown) within the DRAMs. The circuitry generates the internal clock signal by comparing the voltage of the clock signal with the reference voltage V.sub.ref.
Unfortunately, the single-ended clock driver circuit 9 produces clock signals with relatively poor timing accuracy, i.e., "clock jitter," especially at higher clock frequencies. There are several causes for the clock jitter. First, the voltage of the clock signal is dependent on the voltage V.sub.Term, which typically suffers from significant "noise" (i.e., rapid voltage fluctuations). The noise in the voltage V.sub.Term may be caused, for example, by the switching on and off of numerous transistors in the system that are coupled to the voltage source. Second, the internal clock signal that is derived from the clock signal is dependent on the voltage V.sub.Ref, which is also noise-prone for similar reasons.
A third cause for the clock jitter are the primary and secondary reflections of the clock signal produced on the clock line 8. Primary reflections are reflections of the clock signal produced along the conductor 10 by taps along the conductor at which the DRAMs 11 are connected and by the termination resistor R.sub.T. The reflections travel back towards the clock driver circuit 9. These reflections occur because of an impedance mismatch or discontinuity in the clock line 8 caused by the taps and/or the termination resistor. The primary reflections in turn cause secondary reflections to occur at the output of the clock driver circuit 9. The secondary reflections occur because the output impedance of the clock driver circuit 9, which acts as a high output impedance current source, is significantly greater than the loaded impedance Z.sub.0 of the clock line 8. The secondary reflections travel back down the conductor 10, thereby disturbing the clock signal waveform and causing jitter in the clock signal received by the DFIAMs 11.
In view of the shortcomings of the prior art, it is an object of the present invention to provide a clock driver circuit that generates clock signals with minimal clock jitter despite the presence of noisy voltage supply signals.
It is another object of the present invention to provide a clock driver circuit that presents an output impedance that closely matches the loaded impedance of the clock line so as to minimize secondary reflections on the clock line.
More generally, it is an object of the present invention to provide an output driver circuit that generates a signal on a signal line with these characteristics.